In this way, the electrode metal would contact the graphene channel directly. To further improve the device performances, we utilized atomic layer etching (ALE) technique to remove the MoS 2 beneath the source/drain electrodes. IPGTs with a 300 nm gate-channel separation were fabricated on the MoS 2/graphene film using the e-beam lithography. In this work, we fabricated and characterized in-plane gate transistors (IPGTs) based on molybdenum disulfide (MoS 2)/graphene hetero-structure 25, 26, 27. Together with in-plane gates, the 2D channel passivated by epitaxially grown 2D materials may exhibit optimized performances. Nevertheless, the results still demonstrated that a less conductive 2D material may act as the passivation layer for the 2D channel. However, due to the high growth temperatures of h-BN, sequential mechanical exfoliations of different 2D materials instead of epitaxial growth are usually adopted for such hetero-structures, which may introduce additional contaminations to the 2D material interfaces. Similar to being interfacial layers on the SiO 2, h-BN is also adopted as the passivation layers to 2D material devices 23, 24. Without extra chemical bonding, passivation based on another 2D material may bring the least impact to the 2D channel. A passivation layer is still necessary to protect the channel from environments. Water or oxygen molecules in air may attach to the 2D channel and degrade the device performance. However, without top covering, the channel is exposed to the atmosphere. This device architecture may lower the influence of dielectric/2D-material interfaces on 2D channels. In previous works, it has been shown that transistors with in-plane gates can be realized on compound semiconductors 21, 22. The other possible solution may be the adoption of different device architecture without dielectric/2D-material interfaces. Due to the atomically flat surface and wide bandgap value of h-BN, superior device performances are obtained for such bottom-gate graphene transistors 19, 20. One possible approach to solve this problem is to use dielectric 2D materials such as hexagonal boron nitride (h-BN) as the interface layers to the SiO 2 dielectrics. Since the top gate scheme is the most common device architecture adopted for field-effect transistors (FETs) in industry, a poor dielectric/2D-material interface can easily degrade the performance of thin 2D transistors 16, 17, 18. With an active region down to nanoscale, little room is left for 2D channels vertically. However, the characteristics of thin body also hinder the practical usage of 2D materials. On the hand, since the unique material characteristics of 2D materials can be observed in a few atomic layers, devices with ultra-thin bodies can be fabricated on these materials, making them a promising candidate for advanced electronics with reduced linewidth 12, 13, 14, 15. Despite its zero-bandgap nature, the high mobility of the first discovered 2D material, graphene, have demonstrated its potential in the application of radio-frequency devices 7, 8, 9, 10, 11. The epitaxial process also was key to the development of ICs.The high mobility and bright luminescence of two-dimensional (2D) materials are their major advantages in device applications 1, 2, 3, 4, 5, 6. Sylvania's germanium epitaxial transistors resemble the 2N702 and 2N711, with improved performance in saturation voltage and switching time. They are capable of delivering 0.5 w power output with 10-db gain at 70 mc. Breakdown voltages are in the order of 90 v and storage time as low as 12 nsec. Motorola Semiconductor is offering a low-cost type 2N834 silicon-mesa transistor. The typical storage time for the epitaxial unit is less than 100 nsec, while for the 2N697 it is 400 nsec. The typical collector-to-emitter saturation voltage at 150 ma has been reduced by a factor of two. Rheem Semiconductor's RT409 silicon unit is similar to the 2N697, with a 60-v collector breakdown. Three epitaxial transistors were recently introduced: The basic process consists of depositing a thin (about 1/2-mil) layer of high resistivity semiconductor material on a thicker substrate of low resistivity material. The major advantages of epitaxial transistors are the virtual elimination of the collector series resistance and a large decrease in storage and turn-off times.
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